1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are currently indispensable key devices for electronic devices. Semiconductor memory devices are mainly categorized into volatile memories represented by SRAMs and DRAMs and non-volatile memories represented by flash memories. Memory data in SRAMs and DRAMs can be read out and written at a high speed and at random, and thus, they are memories that can be very easily handled, but they are volatile memories that cannot hold data without a power supply.
SRAMs have better performance than DRAMs in the speed of operation and the holding of data as volatile memories, but the area occupied by the device is greater and the cost is higher, and therefore, the majority of the market is occupied by DRAMs, of which the cost is lower. In DRAMs, each memory cell is made up of one transistor and one capacitor, and the degree of integration of the memory has increased as the process dimensions have been scaled down. In recent years, however, the limits of miniaturization have been pointed out mainly due to the difficulty in the scaling down of the capacitor, and under such circumstances, research has been performed as in Documents 1 to 4 cited below on one-transistor type DRAMs where a majority carrier is accumulated in the channel body of the transistor so that the memory is held.    Document 1: Japanese Unexamined Patent Publication No. 2003-31693    Document 2: Japanese Unexamined Patent Publication No. 2005-79314    Document 3: U.S. Pat. No. 7,085,156    Document 4: U.S. Pat. No. 7,085,153
FIGS. 1A to 1C are schematic cross-sectional diagrams showing the device structure of a one-transistor type DRAM described in the above Documents 1 to 4. An insulating film 102 is formed on a semiconductor substrate 101, and an n type source region 103, an n type drain region 104 and a p type channel body region 105 of a MISFET are formed in a semiconductor layer electrically separated from the semiconductor substrate 101 by means of the insulating film 102, that is to say, in a so-called SOI (silicon on insulator) substrate. A gate electrode 107 is formed above the channel body region 105 with a second insulating film 106 in between. Data is stored in two states: a state “1” where a majority carrier (holes) is accumulated excessively in the channel body region 105, and a state “0” where there is no excessive accumulation.
At this time, the state “1” is programmed by operating the MISFET in a pentode region so that a large current from the drain region 104 flows and impact ionization is caused in the vicinity of the drain region 104 (FIG. 1A). Holes that are generated through this impact ionization and are a majority carrier that is excessively accumulated are held in the channel body region 105. Meanwhile, the state “0” is programmed by applying a voltage between the drain region 104 and the channel body region 105 in the forward direction, so that the excessive holes are released from the channel body region 105 (FIG. 1B). The difference between the two states “1” and “0” can be detected as a difference in the threshold voltage of the MISFET. That is to say, a low threshold voltage shows the state where a majority carrier is excessively accumulated, while a high threshold voltage shows the state of no excessive accumulation. When a voltage that is in the middle of the two threshold voltages is applied to the gate electrode, a large current flows in the state where a majority carrier is excessively accumulated and no current flows in the state of no excessive accumulation, and thus, the two states can be distinguished (FIG. 1C). FIG. 2 shows the dependency of the drain current on the gate voltage in the case where a predetermined drain voltage (0.2V) is applied in each state of “1” and “0.”
Meanwhile, most of the non-volatile memories currently available in the market are devices categorized into a flash memory.
Flash memories are non-volatile memories which hold memory even when the power supply is turned off, but there is a limitation in the method for writing and reading out as well as the rate of writing and the number of times of writing, and thus, flash memories are not easy to use as compared to DRAMs and SRAMs.
Therefore, it is common in conventional electronic devices that data stored in a non-volatile memory is shifted to a volatile memory at the start up of the device so that the volatile memory is used as a working memory, and the data in the volatile memory is again stored in the non-volatile memory at the time of shutting down the device.
A non-volatile memory where data can be written and read out at random and without limitation, which is a so-called ideal memory, would be gained by combining the good points of the above described volatile memories and the non-volatile memories. Therefore, implementation thereof has been attempted. MRAMs, FeRAMs, PCRAMs, RRAMs and the like have been researched as non-volatile memories that could be substituted for the flash memory, for example. These are currently in the stage of being developed, and they have better performance than the flash memory in that data can be written at random.
A non-volatile memory where random writing and random reading out are possible can be implemented theoretically by FeRAMs, PCRAMs, RRAMs and MRAMs, but their writing performance is inferior to that of the conventional DRAMs. The number of times where writing is possible has been increasing in PCRAMs and RRAMs year after year, but the number of times of writing is not infinite and is approximately 109 times at the most, and thus, concern remains in securing sufficient reliability as a RAM where writing is always possible.
In PCRAMs and RRAMs, resistance change elements where the resistance value changes through the application of a voltage are used as memory cells for storing information. The resistance change elements have two or more states by controlling the voltage applied between two terminals and the flowing current. In PCRAMs using chalcogenide, for example, the resistance change elements can be switched between a low resistance state, which is a crystal state, and a high resistance state, which is an amorphous state by controlling the applied voltage and the applying time. In addition, in RRAMs using a metal oxide, the resistance change elements can be controlled between a low resistance state and a high resistance state by changing the amount of deficit of oxygen or a metal through the switching between the positive and the negative of the applied voltage or the control of the applied voltage and the load resistance.
FIGS. 3A and 3B show the exemplary properties of a resistance change element using a metal oxide (cobalt oxide or copper oxide, for example) where the resistance change element can be controlled between two states, a low resistance state and a high resistance state by switching the connected load resistance and controlling the applied voltage. FIG. 3A shows voltage current properties and FIG. 3B shows an equivalent circuit. In FIG. 3A, V1 and I1 are respectively a threshold voltage and current that make the high resistance state unstable, and V2 and I2 are respectively a threshold voltage and current that make the low resistance state unstable. When a load resistance R is connected to the resistance change element in a high resistance state and a voltage Va is applied, the voltage V applied to the resistance change element can be represented by Va−RI (I is a current flowing across the element), and therefore, the resistance change element shifts to a certain low resistance state A along the load resistance curve V=Va−RI. In contrast, when a load resistance r is connected to the resistance change element in a low resistance state and a voltage Vb is applied, the resistance change element shifts to a high resistance state B along the load resistance curve V=Vb−rI.
FIG. 4A shows the voltage current properties in the case where the resistance change element is controlled by switching the positive and negative of the voltage, and FIG. 4B shows an equivalent circuit. In the case where the resistance change element is connected to a rectifying element having different resistance values when the applied voltage is switched between positive and negative in such a manner that the resistance is R when a positive voltage is applied and the resistance is r when a negative voltage is applied, for example, the high resistance state can be shifted to a low resistance state C by applying a positive voltage Va, and the low resistance state can be shifted to a high resistance state D by applying a negative voltage Vb′, and thus, a so-called bipolar switch can be implemented. When an oxide of cobalt, nickel or copper is used as the metal oxide, titanium nitride is used for one electrode and tantalum is used for the other electrode, for example, Schottky type rectifying properties are provided between the metal oxide and the tantalum electrode, and thus, a resistance change element capable of performing a bipolar switching operation can be formed.
The properties and the controlling method of the resistance change element of an RRAM are disclosed in detail in Japanese Unexamined Patent Publication 2007-188603.
RRAMs have such advantages that data is written through the application of a voltage, and therefore, the amount of current is very small, thus making the power consumption low; a relatively simple structure makes the cell area smaller, and thus, increases the density (lowering the cost); and the reading out time is as short as that of DRAMs. However, the number of times of possible writing is approximately 109 at the most, though it has been increasing year after year, and thus, no RRAMs can be used as a DRAM where writing is always possible.
Though the number of times of possible writing is greater in FeRAMs than in PCRAMs or RRAMs, it is still difficult for FeRAMs to be substituted for DRAMs due to destructive read out. Though MRAMs theoretically have an infinite number of times of writing, a current directly flows through the tunnel film in a spin injection type MRAM which makes scaling down of the cell size possible, and therefore, deterioration through writing cannot be completely avoided. In addition, it is difficult for PCRAMs to be substituted for a volatile memory due to the low rate of writing.
Therefore, a technology for combining a volatile memory cell and a non-volatile memory cell to form a single memory cell has been examined.
The following Documents 5 and 6 disclose structures where a non-volatile memory cell and an SRAM cell are combined in one memory cell, for example. In these structures, the data stored in the non-volatile memory portion within the memory cell is transferred to the SRAM cell at the time of start up, and the memory cell functions as the SRAM after the transfer.
Document 5: Masashi Takada and five others, “Nonvolatile SRAM based on Phase Change,” IEEE Non-Volatile Semiconductor Memory Workshop, 2006, p. 95
Document 6: Wei Wang and seven others, “Nonvolatile SRAM cell,” Technical Design of International Electron Device Meeting (IEDM), 2006, p. 785
Document 5 describes a structure where a PCRAM cell and an SRAM cell are combined to form one memory cell unit, and Document 6 describes a structure where an RRAM cell and an SRAM cell are combined to form one memory cell unit, and these have both a function of making random writing and reading out possible and a function of a non-volatile memory that can hold the memory when the power supply is turned off. However, the structures are based on the structure of an SRAM circuit, and therefore, the size of the memory is great and the cost is high, thus making it difficult for the structures to be substituted for multipurpose DRAMs or DRAMs mixed in system LSIs.
Meanwhile, conventional standard DRAMs are made up of 1T1C type memory cell units where a control transistor and a capacitor are connected in series. It is theoretically difficult to combine a circuit structure for holding information when a charge is accumulated in a capacitor and a circuit structure for holding information through a change in the resistance value, as in PCRAMs and RRAMs. This is because in the case where a resistance change element and a capacitor are connected in series, the difference in the potential between the two ends of the resistance change element becomes zero with no current flowing when a certain amount of charge is accumulated in the capacitor. In addition, both in PCRAMs and RRAMs, only the amount of charge accumulated in the capacitor in the DRAM cells is too small to change the resistance value for writing. In the case where a resistance change element and a capacitor are connected in parallel, the charge accumulated in the capacitor flows out through the resistance change element, and therefore, information cannot be held. Though it may be necessary to add another transistor to the memory cell units, the circuit area is made large, which causes an increase in the cost.
In contrast, SOI-DRAMs can be regarded as a volatile resistance change element with three terminals in that the stored information appears as a difference in the threshold voltage, that is to say, a difference in the channel resistance between transistors, and thus, the present inventor conducted diligent research and focused on the fact that the matching level is high for the combination with a resistance change element. The allocation ratio of the voltages applied to an SOI-DRAM cell and a resistance change element can be changed by controlling the voltage applied to a gate terminal, which is the third terminal, and therefore, it is theoretically possible to transfer information stored in the SOI-DRAM cell and the resistance change element mutually. However, unless the properties of the resistance change element and the properties of the SOI-DRAM are both understood in detail, malfunctioning occurs such that information in the resistance change element is written when information stored in the SOI-DRAM is written, and therefore, they cannot be normally operated as a memory.